1. Field of the Invention
The present invention relates to a recording format usable for recording information on an information recording medium, and a technology for recording or reproducing information in accordance with the recording format.
2. Description of the Related Art
Recently, research and development of high density optical discs has been actively conducted. Currently, for example, Blu-ray Disc (BD) has been proposed and put into practice, and is used for recording digital broadcast or the like. Optical discs are now establishing their position as an important information medium (see “Zukai Blu-ray Disc Dokuhon” (Blu-ray Handbook with Diagrams) published by Ohmsha, Ltd.). For further increasing the density, research and development is being performed for providing a recording density higher than that of the BD to expand the recording capacity.
FIG. 17 shows an example of a conventional recording format. Recording data is recorded in units of blocks obtained by performing error correction coding processing at every prescribed data amount. A block includes a run-in area used for synchronization detection during reproduction provided at the start thereof, and a data area including the recording data. The data area is divided into a plurality of sectors, and each sector is further divided into a plurality of frames. At the start of each frame, a frame synchronization pattern including a prescribed bit pattern and a synchronization ID pattern unique to the respective frame is located. After the frame synchronization pattern, a bit pattern obtained by modulating the recording data in accordance with a prescribed modulation rule is recorded.
For the BD practically used today, the 1-7 modulation code is adopted, and the shortest bit length is 2 T. The spatial frequency of 2 T is close to the limit of the optical resolving power and corresponds to 80% with respect to the cutoff frequency of the optical transfer function (OTF) of the BD. Where the maximum amplitude detectable for various bit lengths is 100%, the amplitude of the reproduction signal of 2 T is as small as 10% thereof.
FIG. 18 shows the relationship between the optical resolving power of the BD and the shortest bit length 2 T. When the shortest bit length is close to the OTF cutoff frequency, proximate recording marks or even proximate spaces are encompassed in the optical spot. Therefore, the amplitude of the reproduction signal is reduced and also the waveform is distorted by the inter-code interference. Against such amplitude reduction and waveform distortion, the data detection precision is conventionally improved by using a PRML (Partial Response Maximum Likelihood) technology using an adaptive equalization technology and a maximum likelihood decoding technology such as Viterbi decoding.
FIG. 19 shows a structure of a conventional optical disc apparatus 1100. The optical disc apparatus 1100 includes an optical head 1001, a motor 1002, a servo circuit 1003, an address reproducing circuit 1004, a CPU 1005, a run-in generation circuit 1006, a data modulation circuit 1007, a recording control circuit 1008, a data signal extraction circuit 1009, a reproduction clock generation PLL circuit 1010, an adaptive equalization circuit 1011, and a data demodulation circuit 1012. In the figure, an optical disc 1000 on which data is recordable in a reproduceable format is shown.
The optical head 1001 irradiates the optical disc 1000 with a light beam for performing data recording or data reproduction. The motor 1002 rotates the optical disc 1000 at a prescribed rotation rate.
Based on a reproduction signal obtained from the optical head 1001, the servo circuit 1003 appropriately controls the position of the optical head 1001 for outputting the light beam and the rotation rate of the motor 1002.
The address reproducing circuit 1004 reproduces address information pre-recorded on a track of the optical disc 1000, which is included in the detected reproduction signal.
The CPU 1005 controls the entire apparatus.
The run-in generation circuit 1006 generates a bit pattern for the run-in area.
The data modulation circuit 1007 generates a bit pattern obtained by performing error correction coding processing and modulation on recording data.
The recording control circuit 1008 controls the intensity of the light beam from the optical head 1001 such that the run-in bit pattern and the bit pattern of the recording data are recorded on a block at a specified address.
The data signal extraction circuit 1009 extracts a data signal based on the recording data from the reproduction signal.
The reproduction clock generation PLL circuit 1010 generates a reproduction clock bit-synchronized to the extracted data signal.
The adaptive equalization circuit 1011 appropriately binarizes the data signal including amplitude reduction or wave distortion by the PRML technology.
The data demodulation circuit 1012 performs demodulation and error correction processing on the binarized data signal in accordance with a prescribed modulation rule to obtain reproduction data.
In order to effectively use the PRML technology in the adaptive equalization circuit 1011, a reproduction clock signal acting as the reference for the operation timing of the adaptive equalization circuit 1011 is required, and also the adaptive equalization circuit 1011 needs to perform adaptive locking control.
A reproduction clock signal is a clock signal synchronized to the bit length of a data signal, and is generated by the reproduction clock generation PLL circuit 1010 which receives the data signal as an input signal. In order to generate a stable reproduction clock signal, it is usually appropriate that the response characteristic of the reproduction clock generation PLL circuit 1010 is set to a frequency which is about one several hundredths to one several tenths of an average spatial frequency of a data signal.
In the meantime, data in the vicinity of the outermost end of the optical disc 1000 may be reproduced by changing the position of the optical disc 1000 to be irradiated with the light beam from the state where data in the vicinity of the innermost end of the optical disc 1000 is being reproduced. For performing such reproduction, it is required to detect the synchronization position with respect to the data signal within a short time. This is required in order not to spoil the accessibility to the data on the optical disc 1000 in the situation where the frequency of the bit length is significantly varied in accordance with the rotation rate of the motor 1002 for rotating the optical disc 1000 or in accordance with the radial position on the optical disc 1000 of the data to be reproduced. For realizing this, the reproduction clock generation PLL circuit 1010 needs to have a capability of locking the frequency and the phase within a short time.
According to the conventional technology, in order to fulfill such a requirement by providing both the stability and the locking capability of the reproduction clock generation PLL circuit 1010 during data reproduction, a run-in area for allowing the reproduction clock generation PLL circuit 1010 to efficiently perform the locking is provided at every prescribed block. As a bit pattern for the run-in area, a single bit pattern shown in, for example, FIG. 17(A) is adopted. In this pattern, the same length bits of 4 T marks and 4 T spaces are continued. Since such a simple bit pattern is known in advance, a frequency error or a phase error can be easily detected and so the reproduction clock generation PLL circuit 1010 can perform the locking stably in a short time.
The adaptive equalization circuit 1011 (FIG. 19) includes an equalization filtering circuit, an adaptive control circuit for controlling a filter coefficient of the equalization filtering circuit, and a Viterbi decoding circuit for binarizing an output from the equalization filtering circuit (none of these is shown).
The adaptive control circuit adaptively controls the filter coefficient of the equalization filtering circuit, such that the signal amplitude or the wave distortion state of the data signal processed by the equalization filtering circuit reaches a target amplitude pre-specified for each bit length, namely, such that the frequency characteristic of the data signal is close to the pre-specified frequency characteristic. The signal amplitude or the wave distortion state of the data signal mainly varies depending on the recording conditions, and therefore it is appropriate that the response characteristic of the adaptive control circuit for controlling the filter coefficient is set to be sufficiently low. The adaptive control circuit is effective for a zone in which the sufficient locking control has been completed, but is not effective for a zone in which the locking control has not been completed. In such a zone, a bit error is likely to occur during the data is decoded by the Viterbi decoding circuit. Therefore, like the above-described reproduction clock generation PLL circuit 1010, the adaptive control circuit needs to perform the locking control within a short time, such that when the position on the track of the optical disc 1000 at which the data is to be reproduced is changed, a stable data reduction state is realized within a short time.
Conventionally, in order to fulfill such a requirement, the following bit pattern is used as the bit pattern for the run-in area: a bit pattern by which all the pre-specified target amplitudes are present, in order to allow the adaptive equalization circuit 1011 to perform the adaptive locking; and further a simple fixed bit pattern in order to allow, with certainty, the reproduction clock generation PLL circuit 1010 to perform the locking.
FIG. 20 shows an ideal signal amplitude of each of signal waveforms of 2 T through 9 T and synchronization sampling points by an ideal reproduction clock signal, where the optical transfer function (OTF) is as shown in FIG. 18 and appropriate equalization processing has been performed. In the example shown here, as shown in FIG. 17(B), the following three bit lengths are used: the shortest bit length 2 T at which the reproduction signal amplitude is minimum, 3 T at which the reproduction signal amplitude is at a medium level, 6 T at which the reproduction signal amplitude is maximum. These three bit lengths are used in order to allow all the target amplitudes to be present. Furthermore, as a simple fixed bit pattern, a bit pattern having a length of 22 T in total including 2 T mark/2 T space/3 T mark/3 T space/6 T mark/6 T space is used, for example.
FIG. 21 shows an ideal signal waveform of a data signal of a repeat unit of 2 T mark/2 T space/3 T mark/3 T space/6 T mark/6 T space and synchronization sampling points by an ideal reproduction clock signal. Owing to this, the reproduction clock generation PLL circuit 1010 can perform the locking and the adaptive equalization circuit 1011 can perform the adaptive locking control both in the run-in area, and so the data recorded after the run-in area can be stably reproduced.
Recently, in order to respond to the demand for a significantly enlarged recording capacity, studies are being made on optical discs having a higher recording density than that of the conventional BD. It has been found that when the length of the recording marks and the inter-mark distances are decreased to obtain a larger recording capacity than the conventional recording capacity, the spatial frequency of the shortest bit length 2 T becomes higher than the OTF cutoff frequency and as a result, the amplitude of a 2 T reproduction signal becomes 0%. For example, FIG. 22 shows an example in which the spatial frequency of 2 T is higher than the OTF cutoff frequency and the amplitude of a 2 T reproduction signal is 0.
As seen from this example, when the bit pattern of a conventional run-in area is used as it is for an optical disc having a higher density than the conventional recording density, the following problem arises. The waveform of a data signal corresponding to marks/spaces having a length of 2 T or a length close to 2 T is largely distorted and so an accurate bit border position cannot be obtained. As a result, the locking by the reproduction clock generation PLL circuit 1010 and the locking by the adaptive equalization circuit 1011 cannot be stably performed.
FIG. 23 shows an ideal signal amplitude of each of signal waveforms of 2 T through 9 T and synchronization sampling points by an ideal reproduction clock signal, where the optical transfer function (OTF) is as shown in FIG. 22 and appropriate equalization processing has been performed. The amplitude of each signal of 3 T or longer is identifiably obtained, but the signal amplitude of 2 T is zero and is not identifiable. FIG. 24 shows an ideal signal waveform of a data signal of a repeat unit of 2 T mark/2 T space/3 T mark/3 T space/6 T mark/6 T space and synchronization sampling points by an ideal reproduction clock signal in such a case. It is seen that because the signal amplitude of 2 T is zero, the mark/space bit border can be accurately obtained only at the border between the 3 T mark and the 3 T space, the border between the 3 T space and the 6 T mark, and the border between the 6 T mark and the 6 T space. In the case where the 2 T mark and the 2 T space are not ideally recorded, the waveforms of 3 T and 6 T adjacent to 2 T are largely distorted. Influenced by this, the border between the 3 T mark and the 3 T space and the border between the 6 T mark and the 6 T space are shifted and cannot be accurately obtained. In a worst case, neither the reproduction clock generation PLL circuit 1010 nor the adaptive equalization circuit 1011 can perform the locking, and the data becomes unreproduceable.
The bit pattern of the conventional run-in area is a repetition of a simple fixed pattern. Therefore, there is another problem that the synchronization for demodulating the data cannot be realized by the data demodulation circuit 1012 and data errors are continued in many consecutive zones. This may occur in the following case. An accurate position in the run-in area cannot be specified, and so the locking by the reproduction clock generation PLL circuit 1010 and the locking by the adaptive equalization circuit 1011 are insufficient. As a result, the frame synchronization pattern of frame 0 which represents the start of data recorded after the run-in area cannot be detected.